The present invention relates to semiconductor integrated circuits, and more particularly, to a clock signal generator for a semiconductor integrated circuit that generates clock signals having a plurality of differing phases.
A conventional synchronous dynamic random access memory (SDRAM) generates an internal clock signal using external clock signals sent from an SDRAM controller and provides the internal clock signal to internal circuits. The SDRAM validates and invalidates the internal clock signal in accordance with an external power-down signal (clock enable signal) sent from the SDRAM controller. More specifically, the generation of the internal clock signal is stopped if the external power-down signal is low regardless of whether the external clock signal is provided. The internal clock signal is generated from the external clock signal when the external power-down signal is high.
FIG. 1 is a schematic block diagram illustrating an internal clock signal generating circuit 100. The generating circuit 100 receives an external clock signal CLK and an external power-down signal (clock enable signal) CKE and uses these signals to generate an internal clock signal CLKMZ. Furthermore, the generating circuit 100 includes a clock signal input buffer 91, a power-down signal input buffer 92, a clock signal monitor input buffer 93, a latch circuit 94, and an enable signal generating circuit 95.
The clock signal input buffer 91, which is preferably a current mirror type input buffer, receives the external clock signal CLK from an SDRAM controller and provides each internal circuit (not shown) with the clock signal CLKMZ, which phase is substantially the same as the external clock signal CLK. The buffer 91 is activated by a high enable signal ENZ and deactivated by a low enable signal ENZ. Thus, the buffer 91 outputs the internal clock signal CLKMZ if the enable signal ENZ is high and inhibits the output of the internal clock signal CLKMZ when the enable signal ENZ is low regardless of whether the external clock signal CLK is provided, as shown in FIG. 2. The enable signal ENZ is generated by the power-down signal input buffer 92, the clock signal monitor input buffer 93, the latch circuit 94, and the enable signal generating circuit 95.
The power-down signal input buffer 92, which is preferably a current mirror type input buffer, receives the external power-down signal CKE from the SDRAM controller and generates a main power-down signal CKEMZ, which phase is substantially the same as the external power-down signal CKE. That is, the buffer 92 outputs a high main power-down signal CKEMZ if the external power-down signal CKE is high (non-power-down state) and outputs a low main power-down signal CKEMZ if the external power-down signal CKE is low (power-down state).
The clock signal monitor input buffer 93, which is preferably a current mirror type input buffer, receives the external clock signal CLK from the SDRAM controller and generates a monitor internal clock signal CLKSZ, which phase is substantially the same as the external clock signal CLK. The buffer 93 is activated when either the main power-down signal CKEMZ or the enable signal ENZ is high and deactivated when both the main power-down signal CKEMZ and the enable signal ENZ are low. Thus, the buffer 93 outputs the monitor internal clock signal CLKSZ when activated and inhibits the output of the monitor internal clock signal CLKSZ when deactivated regardless of whether the external clock signal CLK is provided, as shown in FIG. 2.
The latch circuit 94 latches the main power-down signal CKEMZ when the monitor internal clock signal CLKSZ goes high and outputs the latched main power-down signal CKEMZ as the internal power-down signal CKECZ. Thus, the latch circuit 94 outputs a high or low internal power-down signal CKECZ when the monitor internal clock signal CLKSZ goes high.
The enable signal generating circuit 95 latches the internal power-down signal CKECZ when the monitor internal clock signal CLKSZ goes low and outputs the latched internal power-down signal CKECZ as the enable signal ENZ. Furthermore, the generating circuit 95 outputs the previously latched internal power-down signal CKECZ as the enable signal ENZ when the monitor internal clock signal CLKSZ goes high. In other words, the generating circuit 95 outputs a delayed low enable signal ENZ when the internal power-down signal CKECZ goes low and outputs a delayed high enable signal ENZ when the internal power-down signal CKECZ goes high. Therefore, the clock signal input buffer 91 outputs the internal clock signal CLKMZ when the enable signal ENZ, or the internal power-down signal CKECZ, is high. On the other hand, the buffer 91 does not output the internal clock signal CLKMZ when the internal power-down signal CKECZ is low.
A double-data-rate (DDR)-SDRAM has been proposed to satisfy the recent demand for increasing the speed of a data bus and an SDRAM. The DDR-SDRAM includes a clock signal generating circuit for receiving two external clock signals, each having a phase which differs by 180.degree. from the other, and generating two internal clock signals, each having a phase which differs by 180.degree. from the other, using the two external clock signals. The DDR-SDRAM further includes a first internal circuit section operated in accordance with a first internal clock signal and a second internal circuit section operated in accordance with a second internal clock signal. Data processing is divided between the first and second internal circuit sections to increase the operating speed of the DDR-SDRAM.
In the DDR-SDRAM, it is preferred that the two internal clock signals fluctuate at substantially different timings and that the relationship of the two internal clock signals with respect to the validation and invalidation timing is always constant. In other words, if the relationship between the first and second internal clock signals is always constant, for example, if the first internal clock signal is always validated or invalidated before the second internal clock signal, the number of processes executed by the first internal circuit section is the same as that executed by the second internal circuit section. Accordingly, the first and second internal circuit sections always execute processes under the same conditions.
If the validation and invalidation timings of the first and second internal clock signals change intermittently, the number of processes executed by the first internal circuit section is different from that executed by the second internal circuit section. This results in the processing conditions of the first internal circuit section differing from those of the second internal circuit section and hinders satisfactory processing.
The two internal clock signals are generated by two external clock signal input buffers. The external clock signal input buffers are activated by a high power-down signal and deactivated by a low power-down signal. Thus, the validation or invalidation timing of each internal clock signal is determined by the power-down signal.
However, the shifting of the power-down signal between a high level and a low level is carried out without regard to the external clock signal. Thus, when the power-down signal is shifted, the first internal clock signal may be validated or invalidated before or after the second internal clock signal. That is, the validation and invalidation timings of the first and second internal clock signals changes in accordance with the power-down signal. Therefore, the relationship between the first and second internal clock signals with respect to the validation and invalidation timing is not always constant.
Accordingly, it is an objective of the present invention to provide a semiconductor integrated circuit that always validates and invalidates two internal clock signals with a constant relationship.